Mosfet Chips

Mosfet Chip Heat Transfer Model

Customers need to know Mosfet (metal-oxide-semiconductor field-effect transistor), that is, metal oxide semiconductor field effect transistor, in the working state of the junction temperature. Mosfet's kind is given in Figure 1.


Figure 1 CREE Mosfet physical outline, dimensions 0.0614 x 0.1064 x 0.0223 m3. Wherein the casing refers to the underlying copper plate, and the junction means the Mos chip.

The shell temperature Tc is the temperature at which the bottom of the copper plate corresponds to the position of the Mos chip; the chip temperature, i.e., the junction temperature Tj, is the temperature to be determined. The location of the chip and the geometry of the Mosfet are shown in Figure 2.


Figure 2 Mosfet calculation model diagram. Wherein the casing refers to the underlying copper plate, and the junction means the Mos chip.

We have developed a three-dimensional temperature calculation model MosfetTemp to calculate the required junction temperature. The reason why the use of self-programming because

Mosfet geometry can be reduced to regular rectangular geometry, completely separated by structured meshes
Because Mos and Dio chip thickness is very thin, it is best to simplify the surface power and surface thermal resistance. In the ANSYS Fluent can not achieve surface thermal resistance, that is, a surface unit needs to have two temperatures.
Self-made software is easy to implement the experience of the heat transfer coefficient of training, and ANSYS Fluent does not have this feature.

However, we also do Mosfet's Fluent model, used to calibrate each other and self-programming.


Figure 3 Surface model of Mosfet chip and weld layer. Since the thickness of the chip and the solder layer is extremely low, it is not advisable to use a finite thickness dimension in the three-dimensional model, and the chip and solder layer are reduced to no thickness. However, we still need to keep the chip temperature / the difference between the upper surface temperature Tf2 of the solder layer and the lower surface temperature of the weld layer / the upper surface temperature Tf1 of the copper plate because there is still a limited heat between the soldering layers Tf2 and Tf1 Resistance The graph shows the relationship between the various heat flows (marked with red arrows). (T2-Tf2), the heat flow qsolder, in = h2 (T2-Tf2) + p from the chip into the soldering layer, and the heat flow q2 from the silicon layer (T2) into the chip (Mos chips) The relationship between the heat transfer of the weld layer into the copper plate qsolder, out = hmos (Tf2 - Tf1). Finally, the heat from the copper plate into the ambient temperature qcu, out = ha2 (Tc-Ta2). The so-called Mos resistance is mainly provided by the hmos, so the test case training thermal resistance is mainly training hmos.

In order to ensure the reliability of the results, we compared the results of MosfetTemp and Fluent calculations.


Figure 4 Comparison of MosfetTemp and Fluent under a specific operating condition. We see that, in addition to individual local fluent results of some local defects, the overall results are highly consistent